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Patent Searching and Data


Title:
BUS ARBITRATING DEVICE
Document Type and Number:
Japanese Patent JP2000259556
Kind Code:
A
Abstract:

To secure the bus use opportunity of a low-order device all the time, to set priority so as to generally use it and to automatically cancel the continuous occupancy of a bus by a single device.

This device is constituted so as to arbitrate bus access request signals from a plurality of devices and to permit access to one device. In this case, the device is provided with a means (CPU 202) for setting the priority to devices, a means (CPU 202) for setting the mask time of individual devices, change means (R7-R10 and A11-A14) for masking the bus use request of a device which uses the bus, assigning the other device higher priority and determining the priority set by the order setting means (CPU 202) when all the devices are masked, a means 203 for measuring how long the bus is continuously used and special setting means (203, FF, A3, A31-A34 and R3-R6) for determining the priority of the bus access request of a specified device CPU as the highest order when the measured length reaches a prescribed value.


Inventors:
YAMADA SHINKO
Application Number:
JP5755899A
Publication Date:
September 22, 2000
Filing Date:
March 04, 1999
Export Citation:
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Assignee:
RICOH KK
International Classes:
G06F13/362; (IPC1-7): G06F13/362
Attorney, Agent or Firm:
Nobuoki Sugi