To provide a bus control system capable of easily performing the bus trace of a microprocessor through a bus interface for monitoring a microprocessor bus and improving reliability.

A microprocessor board 1 is provided with the microprocessor 2, an internal bus 3, a memory 4 connected to the microprocessor 2 through the internal bus 3, a system control register 5 and a bus interface circuit 6, the access to the memory 4, the system control register 5 and the bus interface circuit 6 of the microprocessor 2 is outputted through the bus interface circuit 6 to an external bus 7 and the internal bus 3 is made traceable. At the time of outputting the write data and read data of the microprocessor 2 from the bus interface circuit 6 to the external bus 7, a write timing and read timing are clearly indicated by changing bus interface signals and data are traced from the external bus 7.