To provide an information processing system which realizes more effective PCI bus data transfer by switching effectiveness and ineffectiveness of a delayed transaction function in accordance with bus use efficiency.

This PCI bus controller is provided with a counter 33 which counts bus cycle execution time on a PCI bus 1, a time stamp counter 34 which counts a certain fixed interval and a register 35 which stores data that is compared with count value of the counter 33 and a comparator 36 which compares the value of the counter 33 with value of the register 35 and has a function which switches so that delayed transaction processing may be nullified when the ratio of bus cycle execution time within a certain decided time falls below preliminarily set value and that it may be made ineffective when it exceeds the value conversely.