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Patent Searching and Data


Title:
BUS CONTROLLER
Document Type and Number:
Japanese Patent JPS6446862
Kind Code:
A
Abstract:

PURPOSE: To shorten the time during which a GP-IB (general-purpose interface bus) is occupied by a talker in a data transfer by outputting an end signal after detecting the coincidence between each output address value obtained at the DMA transfer and the final address value of the DMA transfer data set previously so that the DMA transfer is carried out up to the final byte.

CONSTITUTION: When a DMA controller 11 transfers the data on the final address, a DMA transfer end control means 13 detects the coincidence between the final address value 18 set previously and the address value 17 of an address bus 15. Then an interruption end signal 19 is outputted to a general-purpose bus 14. In such a way, a means is provided to detect the end of the DMA transfer so that the DMA transfer is thoroughly carried out up to the final byte. Thus it is possible to shorten the time during which the GP-IB is occupied by a talker in the data transfer with no intervention of software. As a result, another talker can use early the GP-IB.


Inventors:
SUGIMOTO MINAKO
Application Number:
JP20338387A
Publication Date:
February 21, 1989
Filing Date:
August 18, 1987
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F13/32; G06F13/28; (IPC1-7): G06F13/28; H04L11/00
Attorney, Agent or Firm:
Yoshiyuki Osuga