PURPOSE: To suppress the bus errors caused by a high speed operation at re- execution of a bus cycle and to carry out a correct bus cycle by reducing the bus cycle executing conditions including the operating frequency, the wait frequency, etc., in re-execution of the bus cycle.

CONSTITUTION: In a normal cycle state, a microprocessor MPU 1 executes the bus cycles among the clocks S0 - S7. A bus error detecting part 2 detects an error of a system bus 6 and outputs an error signal 7. The MPU 1 receives the signal 7 and completes the bus cycle under execution to execute again the bus cycle after holding it once. Then the MPU 1 basically executes again the bus cycles up to the clocks S0 - S7. In this case, however, the MPU 1 puts a wait state SW between the clocks S4 and S5. As a result, the bus cycle time is increased and therefore the bus cycle executing conditions are reduced. Then the bus errors caused by a high speed operation can be suppressed at the time of re-execution of the bus cycle.