Title:
BUS CYCLE TIME CONTROL CIRCUIT AND BUS CYCLE PROCESSING METHOD
Document Type and Number:
Japanese Patent JPH08137783
Kind Code:
A
Abstract:
PURPOSE: To operate a system by means of optimum access speed by effectively utilizing the characteristic of respective devices and also eliminating waste to take excess of margins.
CONSTITUTION: A system is constituted by judging access speed by which high speed access is enabled to be executed by CPU 1 and a memory 2 in a present usage environment state based on the peripheral temp. of CPU 1 and the memory 2 and a power source voltage conducted in CPU 1 and variably controlling a wait number for inserting a bus cycle so as to make it optimum for the bus cycle by a wait control means 3.
Inventors:
HARA TOSHIMASA
Application Number:
JP28016794A
Publication Date:
May 31, 1996
Filing Date:
November 15, 1994
Export Citation:
Assignee:
CANON KK
International Classes:
G06F13/16; G06F12/00; G06F13/42; (IPC1-7): G06F13/16
Attorney, Agent or Firm:
Masataka Kobayashi