PURPOSE: To limit the number of synchronous switching bits by deciding the number of bits which vary in value before and after a clock, inverting and outputting all original data at a time with a next clock and outputting a data polarity flag, and inverting received data on a reception side corresponding to the value of the polarity flag and inputting the data.

CONSTITUTION: On the transmission side, a D flip-flop 20 delays data 10 by one clock and a logic circuit 23 exclusively ORs the original data 10 with data 12, which are outputted one clock later, bit by bit. In a majority decision circuit A, the output of a comparator 26 becomes 1 only when '1' bits among all N bits become more than N/2 bits. At this time, a selector 21 outputs the inverted data 15 of the original data 15. Further, the data polarity flag becomes 1 only when the data 15 are inverted to the data 10. On the reception side, the original data are restored on the basis of the polarity flag 16.