Title:
The CMOS logic circuit which uses passive internal body tie bias
Document Type and Number:
Japanese Patent JP6279885
Kind Code:
B2
Abstract:
This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.
Inventors:
Paul S. Fetuna
Weston Roper
James Dee Seefeld
Weston Roper
James Dee Seefeld
Application Number:
JP2013233682A
Publication Date:
February 14, 2018
Filing Date:
November 12, 2013
Export Citation:
Assignee:
Honeywell International Inc.
International Classes:
H01L21/822; H03K19/094; H01L27/04
Domestic Patent References:
| JP9121152A | ||||
| JP2000101416A |
Foreign References:
| US5821769 | ||||
| WO2008114379A1 | ||||
| US20100007382 | ||||
| US20060006923 |
Attorney, Agent or Firm:
Shinjiro Ono
Yasushi Kobayashi
Shigeo Takeuchi
Osamu Yamamoto
Naoki Kazuma
Yasushi Kobayashi
Shigeo Takeuchi
Osamu Yamamoto
Naoki Kazuma
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