Title:
キャッシュアクセス測定デスキュー
Document Type and Number:
Japanese Patent JP7453360
Kind Code:
B2
Abstract:
A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.
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Inventors:
Paul Moyer
John kelly
John kelly
Application Number:
JP2022522317A
Publication Date:
March 19, 2024
Filing Date:
October 29, 2020
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INCORPORATED
International Classes:
G06F12/121
Domestic Patent References:
| JP2003280987A | ||||
| JP2019516188A | ||||
| JP2019517690A |
Foreign References:
| US20130151778 | ||||
| CN101866318A |
Attorney, Agent or Firm:
Yuji Hayakawa
Ryota Sano
Keisuke Murasame
Ryota Sano
Keisuke Murasame