To provide a cache control circuit etc. wherein the using efficiency of a system bus and the throughput of a processor are prevented from being deteriorated even when receiving a large amount of packets by making an FCC to avoid DMA operation before the processor processes BD stored in a cache.

E=1 of BD in burst read transaction is monitored and E=0 of BD in burst write transaction is monitored. When the former is detected, DMA is prohibited. When the latter is detected, DMA is permitted. Therefore, it is detected that the processor has completed processing of BD by the block unit of the cache.