To provide a cache memory control circuit that caches data in a plurality of memory spaces in a cache memory, and reduces power consumption without reducing an operating frequency of a processor or increasing the latency of memory access.

The cache memory control circuit includes a plurality of counters 32a-32d and 34a-34d, which are provided for each of sets 21a-21d and memory spaces A and B, to count data of a corresponding memory space stored in a corresponding set. The cache memory control circuit controls activation of tag memories 38a-38d and data memories 40a-40d of the plurality of sets 21a-21d, according to the count values of the plurality of counters 32a-32d and 34a-34d.