PURPOSE: To provide a cache control system which can reduce deterioration of the cache hit ratio and can attain the satisfactory memory performance in regard of an information processor containing a cache memory to which plural processors can have accesses.

CONSTITUTION: If the memory access request given from a processor does not hit a cache and the corresponding block data is read out of a main storage, the processing which registers the block data in the cache by the functions of a main storage access controller 14 and a cache registration suppressing circuit 15 and according to the presence or absence of a host cache of the access requester. Thus, it is possible to suppress the increase of busy ratio of a cache memory 8 due to the cache registering operation in a cache memory control system.