PURPOSE: To exclude a faulty completion of processing and to attain the automatic degeneration processing by providing the error check bits to both a cache memory and a cache directory respectively, and performing the error checks of the memory and the directory when a data read-out request is fed from a CPU.

CONSTITUTION: A selection signal SEL is set at 1 when the data bits read out of hit detecting circuits 40 and 41 are coincident with an upper address signal ADH and also when both error detecting circuits 32 and 30 and 33 and 31 detect no error. Thus a selection circuit 6 selects the data bits read out of block groups 10 and 11 and outputs a signal DAO to a CPU. In other words, the data bits read out of the groups 10 and 11 are sent to the CPU in response to hit signals HIT0 and HIT1. The signal SEL of logic 1 is supplied to a control circuit in an error storage/control circuit 7. The circuit 7 sends a reply signal RPY to the CPU in response to the signal SEL.