Title:
キャッシュメモリおよびその制御方法
Document Type and Number:
Japanese Patent JP4044585
Kind Code:
B2
Abstract:
The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.
Inventors:
Tetsuya Tanaka
Okabayashi Hazuki
Ryuta Nakanishi
Kiyohara Kazuhiro
Takao Yamamoto
Keisuke Kaneko
Okabayashi Hazuki
Ryuta Nakanishi
Kiyohara Kazuhiro
Takao Yamamoto
Keisuke Kaneko
Application Number:
JP2005515399A
Publication Date:
February 06, 2008
Filing Date:
September 08, 2004
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F12/08; G06F12/12
Domestic Patent References:
| JP10232834A | ||||
| JP6019797A | ||||
| JP8263370A | ||||
| JP4137053A | ||||
| JP4100158A |
Foreign References:
| WO2002008911A1 | ||||
| WO2005029336A1 |
Attorney, Agent or Firm:
Hiromori Arai