PURPOSE: To conduct a test on an instruction cache memory only by means of adding a test mode signal to an instruction decoder by checking the built-in instruction cache memory at the external part of a micro processor.

CONSTITUTION: When a signal 104 comes to '1' and is inputted, the instruction decoder 10 continuously outputs '0' even if the instruction code of a signal 105 comes to any value. A content which is read from the instruction cache memory 6 is inputted to a computing element 17, which outputs data as it is and sets it in a register 18. Then, a program sequencer 12 generates a subsequent address, sequentially reads the instruction cache memory 6 and outputs it to a data address bus 102, namely, the external part of the micro processor. Thus, the test of the instruction cache memory 6 is conducted only by adding the test mode signal for instruction decoding and without adding hardware for the test and without cache access being delayed.