演算装置 - Semiconductor Energy Laboratory Co., Ltd.

Title:

演算装置

Document Type and Number:

Japanese Patent JP7502503

Kind Code:

B2

Abstract:

An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit. The first to third data retention circuits each include a transistor including an oxide semiconductor and a capacitor.

Inventors:

Takahiko Ishizu
Takayuki Ikeda
Atsuo Isobe
Atsushi Miyaguchi
Shunpei Yamazaki

Application Number:

JP2023030844A

Publication Date:

June 18, 2024

Filing Date:

March 01, 2023

Export Citation:

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