PURPOSE: To attain the high-speed control of a digital phase shifter by connecting a memory circuit for phase shifter control signal to a calculating circuit for phase shifter control signal.

CONSTITUTION: Signals Δx and Δy are latched by latch circuits 1 and 4 of a calculating circuit for phase shifter control signal. The calculation is started for phase shift amount at a time point when a calculation start request signal is supplied to a clock generating circuit 15 and synchronously with clocks 1 and 2. The outputs of cumulative addition circuits 13 and 14 are added together by an adder circuit 16 synchronously with clocks 1 and 2, and this calculated value is extracted. At the same time, a correction member is delivered from a correction value memory circuit 18 synchronously with the rise of the clock 1. The phase amounts are delivered from an adder circuit 17 in the prescribed order. While X and Y direction address designating circuits 20 and 21 designate the array grid numbers for extraction of the phase shifter control signal out of a memory circuit for phase shifter control signal is synchronously with the rise of the clock 1. Therefore the calculated position amount is latched by a latch circuit within the memory circuit for phase shifter control signal set a position of an array grid number.