Title:
キャリアの製造方法および半導体ウェーハの研磨方法
Document Type and Number:
Japanese Patent JP7070010
Kind Code:
B2
Abstract:
A carrier, which is capable of facilitating to obtain a semiconductor wafer having a high flatness in the outer peripheral portion after double-side polishing, a method of manufacturing the carrier, a method of evaluating a carrier, and a method of polishing a semiconductor wafer are provided. In a carrier for double-sided polishing, which has a holding hole for holding a semiconductor wafer, the difference between the thickness of the carrier at the position of the inner wall defining the holding hole and the thickness of the carrier from the inner wall to a position 6 mm radially outside of the holding hole is 1 [mu]m or less.
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Inventors:
Takeshi Kuroiwa
Kei Kondo
Kei Kondo
Application Number:
JP2018078691A
Publication Date:
May 18, 2022
Filing Date:
April 16, 2018
Export Citation:
Assignee:
Sumco inc.
International Classes:
H01L21/304; B24B37/28
Domestic Patent References:
| JP2018015877A | ||||
| JP2010023217A | ||||
| JP2011143477A | ||||
| JP2006205265A | ||||
| JP2015174168A | ||||
| JP2004148497A | ||||
| JP2017170536A |
Other References:
安永暢男,はじめての研磨加工,日本,東京電機大学出版局,2011年04月20日,40-41頁、78-79頁
安永暢男、高木純一郎,精密機械加工の原理,日本,工業調査会,2002年10月25日,160-163頁
安永暢男、高木純一郎,精密機械加工の原理,日本,工業調査会,2002年10月25日,160-163頁
Attorney, Agent or Firm:
Kenji Sugimura
Mitsutsugu Sugimura
Keisuke Kawahara
Mitsutsugu Sugimura
Keisuke Kawahara