Title:
CDMA RECEIVER
Document Type and Number:
Japanese Patent JP3479836
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To surely insert a TPC bit into a transmission signal.
SOLUTION: This receiver is provided with a synchronization complementing circuit 4 for generating path delay quantity 11, an SIR-estimating circuit 7 for generating an SIR value 12, a memory 8 for storing a past SIR value 13 generated by the SIR-estimating circuit in the past, and a TPC bit generating circuit 9 for generating a TPC bit 15, based on the path delay quantity 11 and the SIR value 12 and the past SIR value 13. Then, a CDMA receiver 10 can be prevented from being unable to insert the TPC bit 15 into a transmission signal under the monitor of the path delay quantity 11, since the generation time of the latest SIR value 12 is delayed due to the increase of the path delay quantity 11. When the path delay quantity 11 is larger than a threshold, the TPC bit 15 is generated, based on only the past SIR value 13.
Inventors:
Shuzo Yanagi
Application Number:
JP2000282060A
Publication Date:
December 15, 2003
Filing Date:
September 18, 2000
Export Citation:
Assignee:
NEC
International Classes:
H04B7/005; H04B7/26; H04J13/00; H04W52/04; H04W52/22; H04W52/24; H04W56/00; H04W76/02; H04W52/54; (IPC1-7): H04J13/00; H04B7/26; H04Q7/38
Domestic Patent References:
| JP10145293A | ||||
| JP2000165321A | ||||
| JP2000236296A | ||||
| JP114213A | ||||
| JP1051424A | ||||
| JP9312609A | ||||
| JP11284569A | ||||
| JP11505693A |
Other References:
【文献】清尾 俊輔 外2名,「DS-CDMAの適応送信電力制御におけるSIR測定法の検討」,1996年電子情報通信学会ソサイエティ大会講演論文集,1996年 8月30日,1,p.331,B-330
Attorney, Agent or Firm:
Masahiko Desk (2 outside)