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Title:
CHARGE TRANSFER DEVICE
Document Type and Number:
Japanese Patent JPH04133335
Kind Code:
A
Abstract:

PURPOSE: To reduce the electric resistance of the transfer gates and to prevent the waveform from being dull at a high-speed transfer operation by a method wherein a transfer gate in each layer is constituted by forming a polysilicon film, a high-melting-point film or a film containing a high-melting-point metal.

CONSTITUTION: A buried channel 6 is provided on the surface 7a of a P-type silicon substrate 7. Transfer gates 2, 2,... and transfer gates 1, 1,... which are composed of the same layer are provided on it. A silicon oxide film 3 and a silicon nitride film 4 are formed on the surface 7a. The individual transfer gates 1, 2 are formed respectively of polysilicon films 1b, 2b, and of WSi2 film 1a, 2a formed on them. The end of the gates 1 is overlapped with the end of the gates 2, and a transfer efficiency is increased. Oxide films 9 of WSi2 are formed on the upper part and the side part of the gates 2, 2; the part between the gates 1, 2 is insulated electrically. Since the electric resistance of WSi2 is lower than that of polysilicon, it is possible to lower the electric resistance of the individual gates 1, 2. Consequently, it is possible to eliminate dull waveforms at a high-speed transfer operation.


Inventors:
NAGASAWA TSUNEYUKI
ISHIHAMA AKIRA
FUKUOKA KOJI
HORIUCHI YASUNOBU
ADACHI HIROSHI
Application Number:
JP25603890A
Publication Date:
May 07, 1992
Filing Date:
September 25, 1990
Export Citation:
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Assignee:
SHARP KK
International Classes:
H01L21/28; H01L21/339; H01L29/762; (IPC1-7): H01L21/28; H01L21/339; H01L29/796
Attorney, Agent or Firm:
Aoyama Ryo (1 person outside)



 
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