CHARGE TRAP NON-VOLATILE MEMORY STRUCTURE FOR 2 BITS PER TRANSISTOR

Title:

CHARGE TRAP NON-VOLATILE MEMORY STRUCTURE FOR 2 BITS PER TRANSISTOR

Document Type and Number:

Japanese Patent JP2005268805

Kind Code:

A

Abstract:

To provide a charge trap non-volatile memory which can simplify the fabrication process.

There is disclosed a non-volatile memory cell structure utilizing a charge trapping high-k dielectric (22) in the place of a triple film stack. The charge trapping characteristic of the high-k dielectric can be further improved by exposing the high-k dielectric layer (22) to a treatment process such as plasma exposure using excited state oxygen (e.g. oxygen plasma) atmosphere. By using a single layer (22) as the charge trapping gate dielectric, a simple and inexpensive solution is presented that permits device scaling to very small dimensions, together with the ease of device fabrication processes. The fabrication process for the charge trapping high-k gate dielectric of the present invention is also applicable to a bulk device, a TFT device or an SOI device.

Inventors:

YOSHI ONO
CONLEY JOHN F JR
JOSHI POORAN CHANDRA

Application Number:

JP2005080522A

Publication Date:

September 29, 2005

Filing Date:

March 18, 2005

Export Citation:

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Assignee:

SHARP KK

International Classes:

H01L21/8247; H01L21/28; H01L21/336; H01L23/58; H01L27/115; H01L29/51; H01L29/786; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115; H01L29/786; H01L29/788; H01L29/792

Attorney, Agent or Firm:

Hidesaku Yamamoto
Takaaki Yasumura
Takeshi Oshio

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