PURPOSE: To realize the chattering elimination circuit without dispersion in a delay time by providing an exclusive OR gate, a counter, a FF, a clock generating circuit and a counter initial value input section to the chattering elimination circuit.

CONSTITUTION: When an input signal 11 and an inverted output signal 12 are the same, an exclusive OR gate 1 outputs an H level reset signal 13. When the reset signal 13 is logical H, an initial value 'n' is given to a counter 2 by an initial value setting input signal 15. When the input signal 11 changes to logic L and the reset signal 13 goes to L, the count is counted-down by a clock signal 14 from a clock generating circuit 14. When the count changes from 'n' to '0' and the clock signal 14 goes to 'L', a pulse outputted. An FF 3 inverts an output signal 17 by the pulse.