PURPOSE: To enable, the processings extending from mounting to electrically testing IC devices, to be performed in a lump using a chip carrier fitted with a multiplane, by boring holes, which separate leads for connecting wires from leads for electrolytic plating, at the intersecting points of both the kinds of leads.
CONSTITUTION: In a manufacturing process of a multiplane chip carriers substrate fitted with, more concretely speaking, after the plating processes of leads 6 for electrolytic plating, and in concurrence with the process for pushing back chip carriers, more leniently speaking, before or after these processes, bored are long holes 7, each of which includes the intersecting points of the lead 6 and leads 4 for connecting wires. By boring the holes 7, all the leads 4 are separated from others, and the chip carriers 2 come independent of others electrically. Also, the electric tests after IC devices being mounted, can be performed in a lump, in the state of the chip carriers being held by the substrate 1. Thereby, in the state of a multiplane chip carrier being mounted on the substrate, the process extending from mounting to electrically testing the IC devices can be performed in a lump, and the curvature of the substrate in the state of the chip carriers being held on it can be prevented.
WADA KOTARO
TETO AKIRA
| JPH0282594A | 1990-03-23 |