Title:
CIRCUIT ARRANGEMENT AND SOLENOID CONTROL UNIT
Document Type and Number:
Japanese Patent JP2023120473
Kind Code:
A
Abstract:
To provide a circuit arrangement in which the voltage at one end or the other end of a shunt resistor is not directly applied to a switch for offset detection.SOLUTION: A current sense amplifier circuit 120 of a circuit arrangement 100 includes: an operational amplifier OPA; a first resistor RIP provided between one end of a shunt resistor 12 and a first node NPC; a first switch SPC provided between the first node NPC and a first input node NIP; a second resistor RIN provided between the other end of the shunt resistor 12 and a second node NNC; a second switch SNC provided between the second node NNC and a second input node NIN; a third resistor RPT provided between a constant voltage node and a third node NPT; a third switch SPT provided between the third node NPT and the first node NIP; a fourth resistor RNT provided between the constant voltage node and a fourth node NNT; and a fourth switch SNT provided between the fourth node NNT and the second input node NIN.SELECTED DRAWING: Figure 4
Inventors:
ISHIMARU HIROSHI
FUTAMURA YOSHIHIKO
FUTAMURA YOSHIHIKO
Application Number:
JP2022023368A
Publication Date:
August 30, 2023
Filing Date:
February 18, 2022
Export Citation:
Assignee:
SEIKO EPSON CORP
International Classes:
H03F3/34; G01R15/00; G01R19/00; H01F7/18; H03F1/30; H03F3/45
Attorney, Agent or Firm:
Noboru Takekoshi
Hajime Inoue
Yasushi Kuroda
Hiroaki Nishikawa
Hajime Inoue
Yasushi Kuroda
Hiroaki Nishikawa