PURPOSE: To prevent an error based on out of synchronism from occurring at a receiving side, by reading out successively an asynchronous signal from a start bit, in response to a pulse generated at each prescribed interval equal to one word length of the asynchronous signal.

CONSTITUTION: A signal of a frequency divider 22 is interleft at each word length interval of data at a counter 23 and a pulse C is produced and given to a flip-flop 24. A transmission data SD is loaded to a register 31, read up to the stop bit, then a signal (a) at a terminal DR goes to "1", a data of the register 31 is transferred to a register 32 and loaded to a register 33 via an external wiring 36 from the register 32 at the same time. When the pulse C rises from "0" to "1" in this state, a Q output (d) of the register 24 goes to "0", the data of the register 33 is transferred to the register 34 and transmitted from the start a bit as a signal (f) via a terminal TRO.