Title:
CIRCUIT DEVICE FOR MATCHING AND ADJUSTING BIT RATE OF TWO SIGNALS
Document Type and Number:
Japanese Patent JPH06244827
Kind Code:
A
Abstract:
PURPOSE: To substantially avoid jitter in a read signal. CONSTITUTION: A first signal structured in the format of a frame is written in an elastic memory 6 by a writing counter 7, and read by a reading counter 8. The counting operation of a compensating counter 14 is controlled by identifying circuits 12E, 12F, 12G, forward and backward counter 19, and each kind of gates 11, 13, 17, and 18. The counting state of the compensating counter 14 is compared with the counting state of the reading counter 8 by a phase comparator 16. The output signal of the phase comparator 16 is used for obtaining a clock pulse for the reading counter 8.
Inventors:
RARUFU URUBANSUKII
Application Number:
JP40492790A
Publication Date:
September 02, 1994
Filing Date:
December 21, 1990
Export Citation:
Assignee:
PHILIPS NV
International Classes:
G06F5/12; G06F5/10; H04J3/00; H04J3/07; H04L7/00; (IPC1-7): H04L7/00
Attorney, Agent or Firm:
Toshio Yano (2 outside)