PURPOSE: To form the circuit configuration so that the circuit No. as a result of decision can be sent as a correct circuit No., by scanning plural circuits, deciding the levels, writing them in the memory, and sending out a scanning signal which has been delayed from the address of the memory by "1", as a circuit No.
CONSTITUTION: The selective circuits SL1WSL4 are scanned by the scanning circuit SCN which counts the clock CLK and outputs a scanning signal. The circuits #1W#8 are selected by the switch circuit SW, are decided by the level decision part LVD, and the result of decision is stored in the memory MEM. MEM is accessed by making the scanning signals Q0WQ2 the address, and the circuit No. is shifted by "1". Therefore, the circuit No. according to the memory contents which have been delayed by 1 clock by the response register ANS is sent out. In this way, even if the circuit No. and the scanning signal are shifted, a correct circuit No. according to the result of decision can be sent out.
NAKAMURA SHIGERU
YAMAZAKI KIYOHIRO
