Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
CLEARANCE CHECK METHOD IN CAD FOR PRINTED CIRCUIT BOARD AND COMPUTER PROGRAM
Document Type and Number:
Japanese Patent JP2003216680
Kind Code:
A
Abstract:

To provide a clearance check method to suppress any cross-talk noises between copper foil patterns including not only between same layers but also between dissimilar layers.

The copper foil pattern in which a current of a high-speed digital signal of a frequency higher than a predetermined value runs is extracted as an element to be inspected (#102), and the copper foil pattern for a signal in proximity to the element to be inspected in the same copper foil layer as the element to be inspected and the copper foil pattern for signal in proximity to the element to be inspected in the copper foil layer dissimilar from the element to be inspected are extracted as proximity elements, and the minimum distance between the element to be inspected and the proximity elements is obtained (#103). If the minimum distance is smaller than the preset violation distance, the length of the copper foil pattern of the element to be inspected or the proximity elements included in a range in which the distance between the element to be inspected and the proximity element is shorter than the violation distance is obtained as the proximity pattern length (#105), and if the proximity pattern length is larger than the present violation length, the proximity pattern length is detected as a clearance violation (#106 and #107).


Inventors:
MAKINO RYOJI
MIWA SHOHEI
Application Number:
JP2002008643A
Publication Date:
July 31, 2003
Filing Date:
January 17, 2002
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
FUJITSU TEN LTD
International Classes:
G06F17/50; H05K3/00; H05K3/46; (IPC1-7): G06F17/50; H05K3/00; H05K3/46
Attorney, Agent or Firm:
Kubo Yukio