Title:
CLEARING DEVICE FOR CASH STORE
Document Type and Number:
Japanese Patent JPS5580875
Kind Code:
A
Abstract:
A processor has a cache store 26, of 512 locations each including 4 levels each of which stores 1 block, each level of each location having a respective full/empty flip- flop associated with it in control logic 38. A primary directory has 512 columns each of 4 levels to store the section addresses of the blocks in the cache store 26 - each section of main memory contains 512 blocks. An absolute address of section address + block address within the section has its block address used to look up the 4 section addresses in the corresponding column of the directory; a match with the absolute section address indicates the required block is in cache and identifies its level. A duplicate directory 52 duplicates the contents of primary directory 32. Writes from other sources have their addresses checked against the duplicate directory. If there is a match, the corresponding full/empty flip-flop associated with the primary directory and cache is cleared, so that the block which has been changed by the write is effectively removed from the cache system.
Inventors:
JIYON BII KUREIN
RONARUDO II RANGU
TOOMASU AARU OORIN
RONARUDO II RANGU
TOOMASU AARU OORIN
Application Number:
JP16073179A
Publication Date:
June 18, 1980
Filing Date:
December 11, 1979
Export Citation:
Assignee:
HONEYWELL INF SYSTEMS
International Classes:
G06F12/08; G06F12/0817; (IPC1-7): G06F13/00; G11C9/06