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Title:
CLEARING METHOD OF SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS59124084
Kind Code:
A
Abstract:

PURPOSE: To clear memory cell instantaneously by making the memory cell asymmetrical, and cutting off holding current flowing through word line connected to all memory cell and then feeding the current again.

CONSTITUTION: Memory cells MC are substantially asymmetrical owing to variance in resistance value difference between load resistances RL1 and RL2. The output Vc of a control circuit varies in level according to whether a clear signal CL is present or not, and the feeding buses consisting of the transistor (TR) Q3 of a switch and a TRQ4 applied with a reference voltage are switched to turn on and off word lines W- connected to all cells. The TRQ1, etc., turns on by turning on and off the holding current to clear the asymmetrical memory cell, so a semiconductor memory is cleared not bit by bit, but instantaneously.


Inventors:
OOAMI KAZUO
Application Number:
JP23163782A
Publication Date:
July 18, 1984
Filing Date:
December 29, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G11C11/41; G06F12/16; G11C11/34; (IPC1-7): G11C29/00
Attorney, Agent or Firm:
Aoki Akira



 
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