Title:
クロック制御方法及び回路
Document Type and Number:
Japanese Patent JP4562300
Kind Code:
B2
Abstract:
A novel clock control circuit and method in which phase synchronization with respect to an external clock can be realized without recourse to the external clocks. A clock controlling circuit includes a delay circuit sequence comprised of N stages of units each made up of a first delay circuit 10 and a first interior division circuit 11 for delaying the output signal of the first delay circuit, and a phase difference detection circuit 14 for detecting the clock period and the delay time difference of the delay circuit sequence from the input clock IN and a clock END output by the delay circuit sequence as a phase difference of the two signals. A plural number of second interior division circuits 12, fed with an output signal of the first delay circuit, delays a transition edge of an output signal of the first delay circuit by t2-nxT/N to output the delayed signal. The second interior division circuit outputs a signal which makes transition at a timing delayed nxtCK/N as from the start time point of the clock cycle. A synthesis circuit 13 generates a frequency multiplied clock signal which is obtained on equal division of the clock period tCK of the input clock from the input clock IN and the number 1 to numberN-1 third delays circuit.
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Inventors:
Takahiro Saeki
Application Number:
JP2001042191A
Publication Date:
October 13, 2010
Filing Date:
February 19, 2001
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G06F1/08; G06F1/06; G06F1/10; G06F7/68; H03K5/00; H03K5/08; H03K5/13; H03K5/15; H03K7/08; H03L7/00
Domestic Patent References:
| JP114145A | ||||
| JP114146A | ||||
| JP11163689A | ||||
| JP10335994A | ||||
| JP10215153A | ||||
| JP200022524A |
Attorney, Agent or Firm:
Kato Asamichi