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Title:
CLOCK DISCONNECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS6432546
Kind Code:
A
Abstract:

PURPOSE: To improve the operating efficiency of the circuit by detecting whether or not a clock signal from a timing extraction circuit is a prescribed level or below, using the detected output signal as a control voltage so as to control the amplifier circuit of a single ended type thereby quickening the operation of the titled clock disconnecting circuit.

CONSTITUTION: An output clock signal recovered by a timing extraction circuit 1 of the timing disconnecting circuit is extracted, and when the clock signal reaches a prescribed level or below, an output voltage V of a peak detecting circuit 2 of a clock disconnection control circuit 16 is lower than a reference voltage Vref of a comparator 3. In response to the result of comparison of the comparator 3, a transistor TR5 is operated. Through the operation of the TR5, the voltage drop of a resistor 6 of a single end type amplifier 15' is increased to control the base of a TR20 to 0V thereby cutting off the TR20. Then the operation of the clock disconnecting circuit is quickened.


Inventors:
YAGYU MIKITO
Application Number:
JP18913087A
Publication Date:
February 02, 1989
Filing Date:
July 28, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K5/19; H04L7/02; H04L7/027; (IPC1-7): H03K5/19; H04L7/02
Attorney, Agent or Firm:
Uchihara Shin



 
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