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Patent Searching and Data


Title:
CLOCK DISPERSION TIMING ANALYSIS METHOD
Document Type and Number:
Japanese Patent JP2004310567
Kind Code:
A
Abstract:

To ensure an accurate timing analysis by not applying a uniform delay factor but applying a delay factor depending on characteristics of each clock path, to branch clock lines.

With an input of a net list 101, a path-specific delay factor setting step 104 sets a maximum value and minimum value of a delay factor depending on characteristics of each path, in clock paths of a data sending FF and data receiving FF. A timing analysis step 106 uses the net list 101, a constraint file 102, a delay information file 103 and a path-specific delay factor file 105 set in the path-specific delay factor setting step 104 to execute a setup check and a hold check and thereby a timing analysis depending on path characteristics.


Inventors:
TAKAOKA SHOJI
HAMAGUCHI KASUMI
Application Number:
JP2003104906A
Publication Date:
November 04, 2004
Filing Date:
April 09, 2003
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F17/50; H01L21/82; (IPC1-7): G06F17/50; H01L21/82
Attorney, Agent or Firm:
Kazuhide Okada