Title:
CLOCK EXTRACT CIRCUIT AND DECODING CIRCUIT
Document Type and Number:
Japanese Patent JP3440666
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To take synchronization for decoding coded data such as CMI coding by means of a clock with the same frequency as that corresponding to a transmission rate.
SOLUTION: Data A are inverted by an INV1, inverted data B are frequency- divided into 1/2 by a flip-flop(FF), a frequency division signal C is given to a PLL circuit 1, in which a clock D with the same frequency as that corresponding to a transmission speed. The data A pass through a delay section DLY1 and delayed data E are sampled by FFs 2, 3 with the clock D and an inverted clock obtained by inverting the clock D at an INV 2. An AND 1 ANDs outputs F, G of the FFs 2, 3 and an AND2 ANDs an inverting output of the FF2 and an inverting output from a 2nd output terminal the inverse of Q of the FF3, and an OR 1 ORs outputs H, 1 of the ANDs 1, 2. An output of the OR1 is logical 1 when the outputs F, G are coincident and logical 0 when the output F is logical L and the output G is logical H. An output of a FF4 is an NRZ code by allowing the FF4 to sample an output J of the OR1 based on the clock D.
Inventors:
Kenichi Sato
Application Number:
JP33833495A
Publication Date:
August 25, 2003
Filing Date:
December 26, 1995
Export Citation:
Assignee:
KABUSHIKI KAISHA MEIDENSHA
International Classes:
H04L25/49; H04L7/00; H04L7/033; (IPC1-7): H04L7/033; H04L7/00; H04L25/49
Domestic Patent References:
| JP637050A | ||||
| JP63263846A | ||||
| JP541669A | ||||
| JP5304476A |
Attorney, Agent or Firm:
Fujiya Shiga (1 person outside)