To completely synchronize clock edges of clock waveforms of differing frequencies by composing a count value hold part of a sequential circuit, which latches data with both leading and trailing edges of an input clock.

An (n+1)-bit subtracting counter circuit is constituted by using Db1-FF, which is capable of latching data with both leading and trailing edges of a driving clock. A circuit consisting of inverters 14 and 15 and a 2-input NOR gate 16 is provided between stages from ExNOR 12-1 of a 2nd stage to ExNOR 12-n of an (n+1)th stage, and two inputs of ExNOR of a precedent stage and inverted by inverters 14 and 15 respectively and inputted to a two- input NOR gate 16, whose output is set as the other-side inputs of ExNORs 12-2...12-n of 3rd and succeeding stages. The clock signal as the counter output is the output signal from the same FF, so no skew is generated between clock edges.