To obtain a stable output which can freely be varied in duty ratio.

Data corresponding to a high-level and a low-level period of a clock signal are held in registers 10-1 and 10-2. When those data match the counted value of a counter 30, the level of the clock signal 700 is shifted. Consequently, the duty ratio can freely be varied only by varying the values of the data held in the registers. Further, control over the level transition of the clock signal 700 is performed in synchronism with a basic clock CLK, so the stable output can be obtained.