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Patent Searching and Data


Title:
CLOCK GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPS5878219
Kind Code:
A
Abstract:

PURPOSE: To lower a clock frequency when no high-speed processing is required, by making the time constant switchable which determines the clock oscillation frequency, and switching said frequency with a microcomputer.

CONSTITUTION: The circuit oscillates with a time constant determined by a capacity 2 and a resistance 3 when a switch 6 is opened, and the circuit oscillates with a time constant determined by a parallel resistance of the resistance 3 and a resistance 5 and the capacity 2 when the switch 6 is closed. Consequently, the circuit can oscillate with two optional frequencies. That is, the switch 6 is opened and closed by the internal control signal of a microcomputer 4 to switch the clock frequency any time. Thus, the clock frequency is lowered when the high-speed processing is not required, and the power consumption of the microcomputer is held at a small value.


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Inventors:
FUJITA KOUICHI
Application Number:
JP17741481A
Publication Date:
May 11, 1983
Filing Date:
November 04, 1981
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03K3/02; G06F1/04; G06F1/08; (IPC1-7): H03K3/02
Attorney, Agent or Firm:
Shinichi Kusano