PURPOSE: To remove the generation of a large current caused by low frequency by supplying a 2nd clock signal to a dynamic circuit when a 1st clock is less than a prescribed frequency level.

CONSTITUTION: This clock generation control circuit is provided with a clock detecting circuit 102 for detecting whether the frequency of the 1st clock signal is more or less than the prescribed value and outputting a detection signal expressing a detection result, a clock generating circuit 103 for generating the 2nd clock signal more than the prescribed frequency and a selector circuit 101 for selecting the 1st clock signal as an operation clock signal when the detection signal expresses the 1st clock signal more than the prescribed value or the 2nd clock signal as the operation clock signal when the detection signal expresses the 1st clock signal less than the prescribed value. When the 1st clock signal is less than the prescribed frequency value, the circuit 101 supplies the 2nd clock signal outputted from the circuit 103 to a dynamic circuit 6. Consequently, the inflow of a large current into the dynamic circuit 6 can be prevented.