To provide a clock generation circuit capable of avoiding a long-term stop of clock output without adding a circuit for oscillating an auxiliary oscillator and normally operating a circuit in a subsequent stage even in the event of a short-period lock releasing of a PPL circuit.
In this clock generation circuit 10, a selector circuit 15 is controlled by a select signal 1f from a selector control circuit 14, so that the selector circuit outputs an input clock 1a instead of a PLL clock 1b when the period of the PLL circuit 11 being in an unlock state exceeds a predetermined value. Accordingly, addition of a circuit for oscillating the auxiliary oscillator is dispensed with, and frequent clock switching as in the past can be avoided to prevent the unstable operation of the circuit in the subsequent stage.
Osamu Kawamiya
Hiroshi Yamazaki
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