Title:
CLOCK LAYOUT SYSTEM AND METHOD
Document Type and Number:
Japanese Patent JP2005258657
Kind Code:
A
Abstract:
To provide a clock layout system and method capable of designing layout while evaluating the level of congestion due to buffer insertion, so that flip-flops are evenly placed.
The clock layout system includes an F/F identifying part 12b that identifies flip-flops among cells placed in the design area of a logic circuit; a cut-line setting part 12c that divides the design area by means of a first segment; an F/F relocating part 12d that relocates the flip-flops so that the difference in number of flip flops between the divided areas is minimized; and a cell relocating part 12e that relocates the cells other than the flip-flops in the divided areas so that the number of wires crossing the first segment dividing the design area is minimized.
Inventors:
ISHIOKA TAKASHI
Application Number:
JP2004067376A
Publication Date:
September 22, 2005
Filing Date:
March 10, 2004
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G06F17/50; H01L21/82; (IPC1-7): G06F17/50; H01L21/82
Attorney, Agent or Firm:
Hidekazu Miyoshi
Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu
Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu