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Patent Searching and Data


Title:
CLOCK PHASE ADJUSTING CIRCUIT
Document Type and Number:
Japanese Patent JPH0214614
Kind Code:
A
Abstract:

PURPOSE: To exclude the control and the constitution of a complicated system and to simplify the constitution of the entire LSI by integrating a clock phase adjustment circuit to a branch point of a flip-flop(FF) required in the LSI.

CONSTITUTION: The clock system is selected to be a system 1 and a clock phase adjustment circuit 11 is provided to a branch point to a FF32 whose delay time is larger than a clock period γ. The same delay as a delay time 3 ns of a data from the pre-stage FF32 is supplied to a clock fed from a chipper 1 of a pulse generating means via a bus 2 by the clock phase adjustment circuit 11 to operate a FF33. If the delay time of the FF is not stored in the clock fed to the input side FF, the clock period is expanded and the constitution and control of the clock system are simplified.


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Inventors:
SERIZAWA ATSUSHI
TOKUMITSU TERUKI
Application Number:
JP16444688A
Publication Date:
January 18, 1990
Filing Date:
July 01, 1988
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03K3/037; H03K5/13; H03K5/133; (IPC1-7): H03K3/037; H03K5/13
Attorney, Agent or Firm:
Yoshishige Tasaka (2 outside)