PURPOSE: To generate and output a clock having arbitrary pulse width regardless of the pulse width of a clock input.

CONSTITUTION: A flip-flop circuit 1 is provided to output a two frequency division signal synchronized to the rise of a clock 101, a flip-flop circuit 2 is provided to ouput a two frequency division signal synchronized to the fall of the clock 101, a signal exchange 3 is provided to exchange and otuput the two inputted frequency division signals through the control signal of a mode register 13, a delay block 6 is provided to input one frequency division signal outputted from the signal exchange 3 and to output an (n) [(n) is a positive integer] pieces of signals to be separated corresponding to a block where an almost 1/2n cycle address phase is delayed, a multiplexer 4 is provided to input this (n) pieces of signals and to selectively output the arbitrary signal through the control signal of the mode register 13, and an EXNOR circuit 5 is provided to input an output signal 104 of the multiplexer 4 and the other frequency division signal outputted from the signal exchange 3 and to output a clock 105 shaping the pulse width.