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Title:
CLOCK REGENERATION SYSTEM
Document Type and Number:
Japanese Patent JPH0368231
Kind Code:
A
Abstract:

PURPOSE: To regenerate a clock whose phase synchronism is quickly pulled in and phase noise is small by providing a clock component extracting part, a reference clock generating part, a correlation part, a clock phase difference calculating part, and a clock output.

CONSTITUTION: A clock component extracting part 1 calculates a difference signal C1 between squares of I and Q signals Si and Sq after regenerating a carrier wave, and a reference clock generating part 12 outputs two orthogonal reference clocks C2 and C3 by a known clock frequency. Each correlation part 15 calculates correlation values C4 and C5 between the clock component C1 and two reference clocks C2 and C3. A clock phase difference calculating part 16 calculates a phase difference P2 by the operation of a prescribed formula and outputs it to a clock output part 20, and the output part 20 obtains a sum P3 of a reference clock phase P1 and the phase difference P2 to take a cosine component, and thereby, a clock CLK of the reception signal is reproduced and outputted. Thus, the clock phase synchronism is quickly pulled in, and the clock is reproduced with a small phase noise after pulling-in.


Inventors:
OKANE TAKEO
SASAOKA SHUICHI
Application Number:
JP20283189A
Publication Date:
March 25, 1991
Filing Date:
August 07, 1989
Export Citation:
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Assignee:
YUSEISHO TSUSHIN SOGO KENK
International Classes:
H04L27/14; H04L7/00; (IPC1-7): H04L7/00; H04L27/14
Domestic Patent References:
JPS6162258A1986-03-31
JPS6328379A
JPS6422119A1989-01-25