PURPOSE: To make a clock frequency variable by constituting an inverting circuit of a comparator, and making the hysteresis width variable.

CONSTITUTION: The output from an output terminal is inputted to the inverting terminal of a comparator 3 being an inverting means via a delay line 2 being a delay means. The noninverting input of the comparator 3 is connected to ground via a variable resistor 4, and a resistor 5 is interposed between the output of the comparator and the noninverting input of the comparator. Moreover, a hysteresis is provided to the comparator 3 by using the resistor 5 and the variable resistor 4, and the width of the hysteresis is varied by varying the variable resistor 4. Thus, a change in a characteristic impedance is eliminated regardless of simple constitution and the clock frequency is made variable.