Title:
CLOCK SYNCHRONIZING CIRCUIT OF MULTI-TRACK TYPE MAGNETIC RECORDING AND REPRODUCING DEVICE
Document Type and Number:
Japanese Patent JPS6061959
Kind Code:
A
Abstract:
PURPOSE:To ensure the easy control of a clock synchronizing circuit by using a voltage controlled oscillator needing control only to a clock synchronizing circuit for >=2 selected tracks, and using a phase locked loop composed of a phase comparator and a phase control circuit to a clock synchronizing circuit of non- selected track. CONSTITUTION:The output of an equalizer 13-2 is applied to a phase comparator 51, and the phase of the output of a changeover switch 35 is compared with the phase of a signal obtained through a delay circuit 52, NAND gate circuits 53 and 54, exclusive OR circuit 55 and a 1/M divider 56. When an output 57 outputs a pulse of ''1'', the circuit 54 opens to supply the output of the circuit 52 to the circuit 55. Thus the number of pulses supplied to the circuit 56 is increased by one. The divider 56 consists of a counter and receives pulses with extra one. Therefore, the output of the divider 56 advances in phase. When an output 58 outputs a pulse of ''1'', both circuits 53 and 54 are closed. Thus the pulses applied to the divider 56 are decreased by one. In such a way, the output of the divider 56 is delayed in phase.
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Inventors:
KATOU MASAAKI
Application Number:
JP16923883A
Publication Date:
April 09, 1985
Filing Date:
September 16, 1983
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
G11B20/14; (IPC1-7): G11B20/14
Attorney, Agent or Firm:
Noriyuki Noriyuki