To provide a clock uninterruptible switching device and method, which can prevent out-of-synchronization from occurring at the time of clock switching using a PLL circuit regardless of degree of phase shift of clocks of two systems.

A phase delay means 13 outputs a delayed clock that is delayed by a value corresponding to a phase of a system clock that is not inputted to a PLL circuit 12 of first and second system clocks. A selector 14 receives the delayed clock outputted from the phase delay means 13 and a clock outputted from the PLL circuit 12, and uses the delayed clock as an operational clock when only clock in one system acting as a currently used system is interrupted, but otherwise uses a clock outputted from the PLL circuit 12 as an operational clock.