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Title:
CMOS AND BIPOLAR DIFFERENTIAL CIRCUIT
Document Type and Number:
Japanese Patent JP2000040926
Kind Code:
A
Abstract:

To obtain CMOS and bipolar differential circuits, which have high practicalness which can be formed on a semiconductor integrated circuit by supplying voltage obtained by performing level shift of one output voltage of a differential pair as control terminal voltage of a transistor constituting the other current source.

In a CMOS differential circuit, MOS transistors M1 and M2, in which their respective sources are connected in common and differential input voltage, is inputted to their gates constitute a 1st differential pair and MOS transistors M4 and M3 constitute a 2nd differential pair. The drains of the transistors M1 and M4 are driven by a constant current source I0, and the drain voltages of the transistors M1 and M4 are subjected to level shift by a level shifting means VLS and are supplied as the gate voltages of MOS transistors M5 and M6, which are current sources that drive the 1st and 2nd differential pairs. The sum current or difference current of drain currents of the transistors M2 and M3 become output currents.


Inventors:
KIMURA KATSUHARU
Application Number:
JP20914798A
Publication Date:
February 08, 2000
Filing Date:
July 24, 1998
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06G7/163; H03F3/45; (IPC1-7): H03F3/45; G06G7/163
Attorney, Agent or Firm:
Asato Kato



 
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