Title:
CMOS MULTIPLIER AND BI-CMOS MULTIPLIER
Document Type and Number:
Japanese Patent JP3196826
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a CMOS multiplier and a Bi-CMOS multiplier which can actualize complete linear operation with simple circuitry configuration.
SOLUTION: Three transistors are driven by a main constant-current source I0 from their drains, the gate of a 1st transistor M1 and the gate of a 2nd transistor M are connected in common, and a 1st input pair are constituted with the gate of a 3rd transistor. A 2nd input pair are composed of the gate of a 4th transistor M4 and the gate of a 5th transistor M5. A current source M10 which is biased by a source follower transistor M9 driven by a subordinate constant-current source Ib is connected to the source of the 3rd transistor, current mirror circuits M7 and M8, and M12 and M13 which are biased by source follower transistors M6 and M11 driven by the subordinate constant- current source are connected to the source of the 1st and 2nd transistors, and an output pair consist are constituted together with a current source.
Inventors:
Katsuji Kimura
Application Number:
JP22857097A
Publication Date:
August 06, 2001
Filing Date:
August 25, 1997
Export Citation:
Assignee:
NEC
International Classes:
G06G7/163; G06G7/164; (IPC1-7): G06G7/163
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)