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Title:
CMOS OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JPH02246517
Kind Code:
A
Abstract:

PURPOSE: To prevent a through current from a plus-side power line to a ground- side power line from flowing out by inhibiting a p channel transistor(TR) and an n channel TR from turning on at the same time even in a transition period wherein a signal varies.

CONSTITUTION: A signal which drives the p channel TR QP is transmitted in the order of 1A, 1C, 1E, and the p channel TR QP and a signal which drives the n side is transmitted in the order of 1A, 1C, 1B, 1D, 1F, and the n channel TR QN; and the n channel TR QN turns on with delay by the difference in length between both the signal transmission paths. Therefore, the (p) channel TR and (n) channel TR never energized simultaneously even in the transition period wherein the signal varies. Consequently, no through current flows from the plus-side power line to the ground-side power line.


Inventors:
KAI MUTSUAKI
Application Number:
JP6624689A
Publication Date:
October 02, 1990
Filing Date:
March 20, 1989
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03K5/151; H03K5/15; H03K17/16; H03K19/0185; H03K19/0948; (IPC1-7): H03K5/15; H03K17/16; H03K19/0185; H03K19/0948
Attorney, Agent or Firm:
Shoji Kashiwaya (1 person outside)



 
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