Title:
CMOS SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH02194646
Kind Code:
A
Abstract:
PURPOSE: To improve productivity while increasing tolerance for depths of well regions and of P- and N-type regions by providing a required diode within the well region.
CONSTITUTION: A diode is constituted by an anode of P+-type diffused regions 12 and a cathode 11 of an N+ type diffused region 11, in an N-type well region 13 formed on the surface of a P-type substrate 10. Accordingly. the region 13 has an N-type double structure except the regions 12 of P-type. In the CMOS semiconductor device thus produced, there is no need for strictly controlling depths of the regions and, therefore, productivity is improved. Further, telerance for depths of the P- and N-type diffused regions is improved and the product quality also can be improved.
Inventors:
OOTA YOSHINORI
YOSHIDA MAKOTO
YOSHIDA MAKOTO
Application Number:
JP1454889A
Publication Date:
August 01, 1990
Filing Date:
January 24, 1989
Export Citation:
Assignee:
SHARP KK
International Classes:
H01L21/8238; H01L27/092; (IPC1-7): H01L27/092
Attorney, Agent or Firm:
Aoyama Ryo (1 person outside)
Previous Patent: SUBSTRATE VOLTAGE CONTROLLING APPARATUS
Next Patent: STACKED SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURE THEREOF
Next Patent: STACKED SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURE THEREOF